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| Name | Last modified | Size | Description |
|---|---|---|---|---|
| Parent Directory | - | ||
| 2010_Filtr_obrazu_Projekt_dyplomowy_inżynierski.pdf | 2017-10-30 04:37 | 1.4M | |
| FIR_coeff.txt | 2021-11-23 15:17 | 1.4K | |
| F_obrazu.rar | 2017-10-30 04:37 | 1.1M | |
| F_obrazu.zip | 2023-01-03 11:54 | 1.4M | |
| HypFiles.zip | 2022-01-11 09:58 | 1.6M | |
| Projekt_FIR.zip | 2021-11-23 18:09 | 148K | |
| TimeSpec.zip | 2016-11-29 12:03 | 19K | |
| TutorVerilog_initial.zip | 2023-11-05 19:21 | 3.5K | |
| UART.zip | 2021-11-19 18:00 | 20K | |
| ZZPSC_MGT_2025.pdf | 2025-10-18 18:41 | 4.0M | |
| ZZPSC_MTLB_2024.pdf | 2024-11-18 09:49 | 4.2M | |
| ZZPSC_TB_2025.pdf | 2025-10-06 07:52 | 2.3M | |
| _old/ | 2021-11-23 18:10 | - | |
| intel_formal_verification_practice_session_0.zip | 2023-11-21 13:06 | 2.2M | |